1. Field of the Invention
This invention relates generally to delay cells and, in particular, to delay cells with substantially constant delays over varying temperatures and voltages.
2. Description of the Related Art
A typical integrated circuit ("IC") includes registers or latches, which act as memory elements. FIG. 1 is a block diagram of an input/output (I/O) register. In FIG. 1, I/O register 100 has a data input port 105, a clock input port 110, and a data output port 115.
The data signal input to the data input port 105 and the clock signal input to the clock input port 110 are typically required to meet certain relative timing specifications. For example, these signals must meet set-up time (T.sub.S) and hold time (T.sub.H) specifications for the I/O register 100. The T.sub.S specification requires that the data signal be present at the data signal input port 105 at least by a time T.sub.S prior to the clock transition. The T.sub.H specification requires that the data signal be held for a time T.sub.H after the clock transition. A positive T.sub.H requires that the data signal be held for some time T.sub.H after the clock transition and increases the time needed for storing data into the I/O register. A T.sub.H of zero would require holding the data until the clock transition. A negative T.sub.H would require holding the data signal until a time T.sub.H before the clock transition. A T.sub.H of zero or less (i.e., a negative T.sub.H) would not increase the time needed to store data into the I/O register. As a result, it is preferable to have a negative T.sub.H or at the least a zero T.sub.H.
In a positive edge triggered system, the clock transition with respect to which T.sub.S and T.sub.H are measured is a positive transition, i.e., a transition from a low value to a high value. Conversely, in a negative edge triggered system, the clock transition with respect to which T.sub.S and T.sub.H are measured is a negative transition, i.e., a transition from a high value to a low value.
The data and clock signals input into the data input port 105 and the clock input port 110, respectively, travel on a data path 106 and a clock path 111, respectively. Generally, the data path is the distance between two I/O registers, which is relatively short. On the other hand, the clock path tends to be relatively long as it can span from one end of the IC to the other. As a result, the delay on clock path 111 tends to be longer than the delay on the data path 106.
As noted above, in order to meet the preferred T.sub.H specification of zero or less, the data signal must be held for a time of zero or more before the clock transition. The data signal corresponding to the next clock period must be received after the end of the hold period for the current data signal in order to prevent prematurely overriding the current data signal. Accordingly, the data signal is delayed by an amount sufficient to account for the difference in delay between the clock path 111 and data path 106 and to meet the above-mentioned condition (i.e., receiving the data signal corresponding to the next clock period after the end of the hold period for the current data signal).
FIG. 2 is a diagram of a delay chain used for delaying the data signal. In FIG. 2, delay chain 200 includes inverters 201 and 202. Inverters 201 and 202 cause the data signal to be delayed sufficiently so as to meet the T.sub.H specification. Inverters 201 and 202 are commonly complementary metal oxide semiconductor (CMOS) inverters. Accordingly, they comprise transistors. Generally, the speed of a transistor is affected by the drive voltage and the temperature of the transistor. The speed of a transistor also depends on the process by which a transistor was made. The speed of the transistor increases with an increase in the drive voltage and decreases with a decrease in the drive voltage of the transistor. Conversely, the speed of the transistor decreases with an increase in the temperature and increases with a decrease in the temperature of the transistor. Finally, based on a number of factors in the manufacturing process, the speed of the transistor varies within a range specified by the manufacturer.
As the speed of the transistors in inverters 201 and 202 varies based on the aforementioned factors, the speed of inverters 201 and 202 also depends on the aforementioned factors. Consequently, the delay caused by inverters 201 and 202 is not constant, but varies based on the aforementioned factors. In order to assure that the delay chain 200 causes the necessary delay for meeting the T.sub.H specification over the range of voltage, temperature, and process conditions that the delay chain may operate under, the delay of delay chain 200 is set such that even under fast conditions (i.e., high voltage, low temperature, and fast process), the data signal corresponding to the next clock period will arrive after the hold period for the current data signal. When the process is slower, the voltage is lower, and/or the temperature is higher, then the delay caused by delay chain 200 is increased. In other words, the hold time condition is improved as the data signal corresponding to the next clock cycle is more likely to arrive after the hold period for the current data signal. However, the set-up time condition is worsened as the set-up time is increased.
FIG. 3 is a diagram of the timing relationship between the clock and data signals. In FIG. 3, wave 310 represents the clock signal, whereas waves 320 and 325 represent the data signal with different delays. Wave 320 represents the data signal with a greater delay in order to meet the T.sub.H specification for high voltage and low temperature conditions. Wave 325 represents the data signal with a smaller delay needed to meet the T.sub.H specification for low voltage and high temperature conditions. The data delay is set long enough to correspond to wave 325 even under the condition of high voltage and low temperature.
Setting the delay of delay chain 200 long enough to meet the T.sub.H specification even under high voltage and low temperature causes the data signal to be slower than it needs to be under all conditions. For example when the process is slow, the voltage is low and temperature is high, the delay of the delay chain 200 is increased. This causes the set-up time to increase. The increase in set-up time may create problems when the device operates at a high frequency. As the frequency of the device is increased, the set-up time constitutes a larger portion of the cycle of the device. This causes the overall speed of the device to slow down. The overall speed of the device is the sum of the set-up time, the clock to output time, and the hold time (if the hold time is positive, i.e., if the data must be held for at time T.sub.H after the clock transition). When the hold time is zero or negative, then the overall speed of the device is the sum of the set-up time and the clock to output time. Accordingly, setting a long delay time for delay chain 200 causes the overall speed of the device to slow.
As a result, there has been a need for delay chains that provide the necessary delay for the data signal while avoiding the above-mentioned shortcomings of the earlier systems. The present invention meets this need.